Mothukuru Sudharshan

I work on the architecture of communication inside chips - how cores talk to each other efficiently as systems scale from a handful of cores to hundreds. My research spans hybrid wired/wireless network-on-chip (WiNoC) topologies, chiplet-based traffic generation, and routing algorithms that reduce congestion and latency under real workloads.

I'm currently pursuing a PhD at BITS Pilani, Dubai Campus under Dr. Satya Jaswanth Badri, working on AI/ML-driven, memory-aware hardware accelerators for intermittency-robust edge intelligence.

Junior Research Fellow - IIT Hyderabad

Oct 2025 – Jul 2026

Synergy: Taking Openness to the Next Level in 6G Networks

Studied 5G architecture using OAI 5G Core and UERANSIM for end-to-end network simulation.
Implemented VoNR using open5GS.

Graduate Project Intern - IIT Guwahati

Jul 2024 – Oct 2025

Performance Optimization of Multi-core Processors using Wireless On-Chip Interconnects

Developed a hybrid 2D mesh WiNoC topology combining wired and wireless links.
Built a hybrid routing algorithm to improve packet delivery across wireless routers.

Summer Intern - IIT Guwahati

May 2024 – Jul 2024

Implementation and Analysis of Multi-Core Architectures using Architectural Modelling

Used Gem5, C++, and Python for architectural simulations.
Implemented Odd-Even and DyXY routing techniques to minimize congestion.

Performance Analysis of Wireless Network-on-Chip

Jul 2024 – Jun 2025

Evaluated packet injection rate and average packet latency, comparing wired and wireless setups under varying traffic conditions.

Chiplet-Based Traffic Generation for Wireless Chiplet Network-on-Chip

Mar 2025

Built a custom traffic generator to simulate congestion across a 4×4 mesh of 16 chiplets, with locality-aware destination selection.

Cache Optimization through Victim Cache Behavior Mimicking in Gem5

Jun 2024

Benchmarked against VIPS and x264 for hit/miss rate comparisons.

Rechargeable Smart Cane using Arduino Nano

May 2023 · Best Project Medal

Modular assistive device with a rechargeable lithium-ion battery to extend usage and reduce maintenance.

Impact of Dual Channel Communication for Wireless Interconnects of Chiplet based Architectures

IEEE Embedded Systems Letters, 2026

doi.org/10.1109/LES.2026.3657364

Impact of Token Variable Slotting in Performance of Hybrid Network-on-Chip

IEEE GCON, 2025

doi.org/10.1109/GCON65540.2025.11173322

Load-Aware Token Passing MAC Protocol for Starvation Control in Wireless Network-on-Chip

ISDCS, 2025 (co-author)

Performance Analysis of Wireless NoC Routers in Handling Inter-core Traffic in Tiled Chip Multicore Processors

ICETESS, 2025 (co-author)

Rechargeable Smart Cane using Arduino Nano

Proceedings of ICICC, 2024

doi.org/10.2139/ssrn.4937982

PhD, Computer Science & Engineering - BITS Pilani, Dubai Campus

Aug 2026 – Present

SelfPowered Edge AI: Intermittency-Robust, Memory-Aware Accelerators for Battery-less Devices - supervisor: Dr. Satya Jaswanth Badri

M.E., Computer Science & Engineering (AI & ML) - Chandigarh University

Aug 2023 – Jul 2025

Performance Optimization of Multicore Processors Using Wireless On-Chip Interconnects - supervisors: Dr. Ruchika Gupta and Dr. John Jose

CGPA 8.06

B.E., Computer Science & Engineering - Chandigarh University

Aug 2019 – Jun 2023

CGPA 7.8

TECHNICAL

Languages: C++

Libraries: C++ STL

Simulation: Gem5 Simulator, OAI 5G Core, UERANSIM, open5GS

POSITIONS OF RESPONSIBILITY

Technical Lead Volunteer - AIORI 1.0 Hackathon & APSIMSS, IIT Guwahati

Dec 16–18, 2024 · Provided technical guidance to participants.

CERTIFICATIONS & ACHIEVEMENTS

UGC NET - Assistant Professor & PhD Jun 2026

National-level eligibility test qualified for Assistant Professor and PhD admission, conducted by UGC.

Junior Research Fellow - Experience Certificate Oct 2025 – Jul 2026

Issued by IIT Hyderabad for research work on the 6G Networks project, "Synergy: Taking Openness to the Next Level."

Advanced Computer Architecture Course Aug–Nov 2024

Completed under Dr. John Jose at IIT Guwahati, covering multi-core and interconnect architecture fundamentals.

NPTEL - Multi-core Computer Architecture Nov 2024

Online certification course from NPTEL (IIT/IISc consortium), completed with a Silver Badge.

Best Project Medal May 2023

Awarded for developing the Rechargeable Smart Cane using Arduino Nano during undergraduate studies.

Open to research collaborations, academic opportunities, or just a conversation about interconnect architecture - feel free to reach out.

OR REACH ME DIRECTLY

Email: sudharshan.m.1916@gmail.com

Phone: +91 70956 31504

LinkedIn: linkedin.com/in/msudha2001